Technology and technique of the CMOS-chip learning experiment

  • Authors: Mishanov R.1
  • Affiliations:
    1. Самарский национальный исследовательский университет им. акад. С.П. Королева
  • Issue: Vol 21, No 1 (2018)
  • Pages: 38-47
  • Section: Articles
  • URL: https://journals.ssau.ru/pwp/article/view/7064
  • ID: 7064

Cite item

Full Text

Abstract

The technique of the learning experiment of the chips with a CMOS structure is considered. The analysis of the constructive-technological features of the 765 series chips have carried out. The connection circuits and schemes of the main parameters measurement during the learning experiment are proposed. A choice of methods and means for the informative parameters control in the investigation tests is studied. The process of the sample size selecting is described. An approach to the development of the routine investigation tests is defined.

About the authors

R.O. Mishanov

Самарский национальный исследовательский университет им. акад. С.П. Королева

Author for correspondence.
Email: mishanov91@bk.ru

References

Supplementary files

Supplementary Files
Action
1. JATS XML

Copyright (c) 2018 Mishanov R.

Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 International License.

СМИ зарегистрировано Федеральной службой по надзору в сфере связи, информационных технологий и массовых коммуникаций (Роскомнадзор).
Регистрационный номер и дата принятия решения о регистрации СМИ: серия ФС 77 - 68199 от 27.12.2016.

This website uses cookies

You consent to our cookies if you continue to use our website.

About Cookies